1. Field of the Invention
This invention relates to processes for fabricating integrated circuits. In particular, the invention involves processes for fabricating MOS or CMOS integrated circuits having a lightly doped drain structure, in which a portion of the source and drain nearest the channel is less strongly doped than other regions of the source and drain.
2. DESCRIPTION OF THE PRIOR ART
Numerous processes are known for the fabrication of MOS or CMOS integrated circuits, for example, self-aligned processes employing polycrystalline silicon gates. Also well known are field effect transistors having "lightly doped drains." In such structures, regions of the source and drain near the channel beneath the gate electrode are less heavily doped than regions of the source and drain further away from the channel. The lower doping near the gate electrode improves the speed and reliability of the device while preventing punch-through. The lighter doping also lowers the gate-source and gate-drain capacitance, and minimizes hot electron injection into the gate.
Unfortunately, lightly doped drain structures typically require additional processing beyond that required for conventional field effect devices such as polysilicon gate MOS structures. In a conventional MOS process, a thin layer of gate oxide is fabricated on a silicon substrate, and an electrode defined on the gate oxide. The electrode is used as a mask for the implantation of the source and drain impurities, which during the same process dope the electrode to lower its resistance. Such conventional MOS processes may also be employed in complementary structures, and have the advantage of being self-aligned. Self-alignment results from using the electrode to define the source and drain regions, thereby assuring that they are properly aligned with the gate electrode without additional masks and their resulting alignment tolerances.
A significant disadvantage of prior art processes for forming lightly doped drain MOS structures is that many such processes require additional masking. For example, in one process the gate is masked with a layer slightly larger than the gate to protect regions of the silicon adjacent the gate electrode. Regions of the silicon further out are then doped with a first process and the mask removed to allow a lighter doping of the regions nearer the gate with a second process.
In another well known lightly doped drain process, a region of silicon dioxide is formed as a spacer along the sides of the gate electrode, and then the silicon heavily doped. The oxide is removed and the thereby exposed regions near the gate, as well as regions further from the gate, then are lightly doped with a second process. Unfortunately, when a metal silicide gate is used, such spacer oxide processes are difficult to control because silicon dioxide on the gate is damaged during the implant so that it will etch as fast as the spacer oxide etches, resulting in its removal from the gate. When the structure is again heated, the silicide will oxidize and corrugate, lowering yields.